Tatsumi discloses a conventional DRAM cell capacitor and manufacturing method in U.S. Pat. No. 5,385,863 issued Jan. 31, 1995, entitled "METHOD OF MANUFACTURING POLYSILICON FILM INCLUDING RECRYSTALLIZATION OF AN AMORPHOUS FILM." As shown in this application HSG silicon is grown on a capacitor storage electrode of simple staked structure.
FIG. 1 shows a conventional art DRAM cell capacitor. Referring to FIG. 1, a conventional art DRAM cell capacitor has a semiconductor substrate 10 whose active and inactive regions are defined by a field oxide layer 12. A pad electrode 14 is formed on the active region of the substrate 10. An interlayer insulating layer 16 is then formed over the field oxide layer 12 including the pad electrode 14. A contact hole 19 is formed through the interlayer insulating layer 16 to an upper surface of the pad electrode 14. A conductive layer is then deposited over the interlayer insulating layer 16 to fill up the contact hole 19, and is then patterned to form a capacitor storage electrode 20. As the storage electrode 20 is formed it's upper surface is perpendicular to each of its sidewalls.
Next, an HSG silicon layer 22 is formed on the capacitor storage electrode 20 so as to increase an effective surface area. Subsequently, so as to accomplish fabrication of the DRAM cell capacitor, the process steps for sequentially forming a dielectric layer and a capacitor top electrode on the capacitor storage electrode should be followed.
Prior to forming the dielectric layer (not shown) on the capacitor storage electrode, a wet etching and washing process should be performed to remove a part of the interlayer insulating layer 16 and to wash the substrate. Generally, the etching process of the interlayer insulating layer 20 uses an etchant that includes a mixture of NH.sub.4 F and HF (which is called a "Lal solution" in the art), and a mixture of NH.sub.3, H.sub.2 O.sub.2 and deionized water (which is called an "sc1 solution" in the arts). The washing process uses an etchant that is a mixture of the scl solution and HF.
During the etching process using scl solution, a part of the HSG silicon layer 22 that is formed on the capacitor storage electrode 20, particularly, on the top edges thereof is apt to be lifted. When this happens, adjacent capacitor storage electrodes may be electrically connected (i.e., short-circuited) with each other by the lifted HSG silicon.
The short-circuit occurring by the lifted HSG between the storage electrodes is shown in FIGS. 2A to 2C. FIG. 2A shows a scanning electron microphotograph (SEM) that illustrates a plan view of the conventional DRAM cell capacitor array, FIG. 2B shows a SEM that illustrates a perspective view of the conventional DRAM cell capacitor array shown in FIG. 2A. FIG. 2C is an enlarged perspective view of the two adjacent DRAM cell capacitors which are indicated by a dotted circle in FIG. 2B.
As is apparent from FIGS. 2A to 2C, after the formation of capacitor storage electrodes, a short-circuit between the capacitor storage electrodes is generated due to an HSG silicon tab 24, which is lifted from the top edges of the respective capacitor storage electrodes. This leads to the failure of DRAM devices.
Lifting the HSG silicon from the storage electrode is caused by the following two reasons: (1.) HSG silicon which is abnormally grown due to the remaining polymers is apt to be lifted during the etching process of the storage electrode. (2.) HSG silicon which is grown at, particularly, the top edges of the storage electrode is apt to be lifted by the following etching and washing process.
Thus, the present invention relates to a method for manufacturing a DRAM cell capacitor wherein HSG silicon is not formed at the top edges of a storage electrode.